View RT5002_4869739.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RT5002 1 ds5002-00 november 2011 www.richtek.com 7 + 1 channel dc/dc pmu with li-ion battery charger for dsc general description the RT5002 is a complete power supply solution for digital still cameras and other handheld devices. it includes a 7+1 channel dc/dc power converter unit, a single-cell li- ion battery charger, and an i 2 c control interface. the power converter unit includes one synchronous step- up converter and three synchronous step-down converters for dsp core, i/o, motor, and memory power supply, one synchronous high voltage step-up converter and one asynchronous inverting converter for ccd bias, one wled driver in either synchronous high voltage step-up or current source operation, and one low quiescent ldo for rtc application. all converters are internally frequency compensated and integrate power mosfets. the power converter unit provides complete protection functions: over current, thermal shutdown, over voltage, over-load, and under voltage protection. the battery charger includes auto power path management (appm). no external mosfets are required. the charger enters sleep mode when power is removed. charging tasks are optimized by using a control algorithm to vary the charge rate, including pre-charge mode, fast charge mode and constant voltage mode. the charge current can also be programmed with an external resistor and modified via the i 2 c control interface. the scope that the battery regulation voltage can be modified via the i 2 c interface depends on the battery temperature. the internal thermal feedback circuitry regulates the die temperature to optimize the charge rate for all ambient temperatures. the charging task will always be terminated in constant voltage mode when the charging current reduces to the termination current of 10% x i chg_fast . the charger includes under voltage and over-voltage protection for the supply input voltage, v in . features power converter unit : one channel lv sync step-up and three channel lv sync step-down up to 95% efficiency one sync step-up and one async inverting for ccd bias one wled driver in either sync step-up or current source operation wled driver with dimming control step-up mode with led open protection (ovp7) one low quiescent ldo with reverse leakage prevention for rtc power supply preset on/off sequence of ch1, ch2, ch3, ch4 (1 3 4 2) two preset on/off sequence of ch5, ch6 (5 6 or 6 5) all power switches integrated with internal compensation all step-up converters with load disconnect wake up impulse to monitor bat and vin plug-in charger unit : 28v maximum rating for vin power selectable power current limit (0.1a / 0.5a / 1.5a) auto power path management (appm) and integrated power mosfets battery charging current control battery regulation voltage control programmable charging current and safe charge timer under voltage and over voltage protection optimized charge rate via thermal feedback interrupt indicator to fault/status events i 2 c control interface : support fast mode up to 400kb/s voltage divider for sensing battery voltage level small 40-lead wqfn package rohs compliant and halogen free applications dsc
RT5002 2 ds5002-00 november 2011 www.richtek.com marking information RT5002zqw : product number ymdnn : date code pin configurations (top view) wqfn-40l 5x5 ordering information note : richtek products are : rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. suitable for use in snpb or pb-free soldering processes. RT5002 zqw ymdnn RT5002 package type qw : wqfn-40l 5x5 (w-type) lead plating system z : eco (ecological element with halogen free and pb free) int fb7 vddm fb4 pvd4 lx4 bats pvd7 lx7 fb1 wake lx5 tssel fb3 pvd3 lx3 en1234 pvd5 fb5 fb2 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 iseta ts vp sda scl pvd6 lx6 vout6 fb6 vref lx1 pvd1 rtcpwr vin sys sys bat bat pvd2 lx2 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 gnd
RT5002 3 ds5002-00 november 2011 www.richtek.com typical application circuit for 4-led application RT5002 4 fb7 10 25 fb5 26 pvd5 lx6 fb6 19 18 ccd -7v 63.4k 10k vref 20 10h 17 vout6 10f x 2 1nf 0.1f 10f x 2 287k 26.1k 27pf ccd 15v 1f lx7 10h 6 1f sys pvd7 5 vin 37 tssel 28 back light adapter /usb 2.2f iseta 11 gnd 41 (exposed pad) pvd2 32 sys 10f scl 15 pvd1 39 2 fb1 lx3 23 fb3 21 pvd4 9 sys rtcpwr 38 super cap pvd3 10f sys 22 14 sda vdd_i 2 c 10f x 2 470k 88.7k motor 5v lx2 31 29 fb2 10f 470k 150k 2.2h 10f 470k 374k 2.2h 10f lx4 8 v core 1v fb4 10 232k 931k 2.2h 10f rtcpwr tssel = vin for 10k ntc r iseta en1234 24 chip enable bat 33, 34 bat + 1f ts 12 vp 13 int 1 interrupt flag v i/o 3.3v wake 30 wake up signal to p ~10k vddm 3 bypass cap 1f pvd6 16 10f sys c12 r9 r10 c13 c15 l6 d1 r11 c17 c16 c18 r12 c19 l7 c20 d2 d3 d4 d5 r13 c21 c22 r16 r17 r18 10k r14 1k r15 1k r7 r8 47pf c11 c10 l4 c8 r5 r6 33pf c7 c6 l3 c5 r3 r4 c4 c3 l2 c1 r1 r2 4.7pf en1234 control ch1 ch3 ch4 ch2 5v 1.8v 1v 3.3v v i/o 3.3v ddrii 1.8v 0.1f c23 bats 7 0.1f c bats bats lx1 40 2.2h sys 10f c2 l1 c24 lx5 27 sys 10h 4.7f l5 c14 sys 35, 36 sys 10f c9 r ntc
RT5002 4 ds5002-00 november 2011 www.richtek.com for 1-led application RT5002 4 fb7 10 25 fb5 26 pvd5 lx6 fb6 19 18 ccd -7v 63.4k vref 20 10h 17 vout6 10f x 2 1nf 0.1f 10f x 2 287k 26.1k ccd 15v 1f lx7 pvd7 5 vin 37 tssel 28 5v adapter /usb 2.2f iseta 11 gnd 41 (exposed pad) pvd2 32 5v scl 15 pvd1 39 2 fb1 lx3 23 ddrii 1.8v fb3 21 pvd4 9 sys rtcpwr 38 super cap pvd3 sys 22 14 sda vdd_i 2 c 10f x 2 470k 88.7k motor 5v lx2 31 29 fb2 10f 470k 150k v i/o 3.3v 2.2h 470k 374k 2.2h 10f lx4 8 v core 1v fb4 10 232k 931k 2.2h rtcpwr tssel = gnd for 100k ntc r iseta en1234 24 chip enable bat 33, 34 bat + 1f ts 12 vp 13 vddm 3 bypass cap 1f 6 back light ~100k pvd6 16 10f sys 10k 27pf c12 r9 r10 c13 c15 l6 d1 r11 c17 c16 c18 r12 c19 d6 c21 c22 r16 r17 r13 r14 1k r15 1k 10f r7 r8 47pf c11 c10 10f l4 c8 r5 r6 33pf c7 c6 l3 10f c5 10f r3 r4 c4 c3 l2 c1 r1 r2 4.7pf en1234 control ch1 ch3 ch4 ch2 5v 1.8v 1v 3.3v int 1 interrupt flag v i/o 3.3v wake 30 wake up signal to p r18 10k 0.1f c23 bats 7 0.1f c bats bats c24 lx1 40 2.2h sys 10f c2 l1 lx5 27 sys 10h 4.7f l5 c14 sys 35, 36 sys 10f c9 r ntc
RT5002 5 ds5002-00 november 2011 www.richtek.com functional pin description pin no. pin name pin function 1 int interrupt indicator open drain output. if any toggle events of ts_fault, pgood, eoc, or safe happen, the output int goes low. after i 2 c register bank address 0x2 is read or power on reset, int goes high. 2 fb1 feedback input of ch1. 3 vddm ic analog power pin. 4 fb7 feedback input of ch7 in step-up mode or current sink pin of ch7 in current source mode. 5 pvd7 power output of ch7 6 lx7 switch node of ch7 in step-up mode. 7 bats output pin of voltage divider for battery voltage level sensing enabled after ch2 soft-start end. bats voltage is about 60% of bat. 8 lx4 switch node of ch4. 9 pvd4 power input of ch4. 10 fb4 feedback input of ch4. 11 iseta charge current set input. connect a resistor (r iseta ) between iseta and gnd. 12 ts temperature sense input. the ts pin connects to a battery?s thermistor to determine whether the battery is too hot or too cold to be charged. if the battery?s temperature is out of range, charging is paused until it re-enters the valid range. ts also detects whether the battery (with ntc) is present or not. 13 vp power output of 3.3v buffer for battery temperature sensing. 14 sda data signal pin of i 2 c interface. 15 scl clock signal pin of i 2 c interface. 16 pvd6 power input of ch6. 17 lx6 switch node of ch6. 18 vout6 sense input of ch6 inverting output node. 19 fb6 feedback input of ch6. 20 vref 1.8v reference output. 21 fb3 feedback input of ch3. 22 pvd3 power input of ch3. 23 lx3 switch node of ch3. 24 en1234 enable pin of ch1, ch2, ch3, and ch4. 25 fb5 feedback input of ch5. 26 pvd5 power output of ch5. 27 lx5 switch node of ch5. 28 tssel input pin to select temperature sensing thresholds. thresholds of tssel = h are 60% and 38% of vp voltage. thresholds of tssel = l are 74% and 28% of vp voltage. 29 fb2 feedback input of ch2. 30 wake wake-up impulse push-pull output. if vin or bat plug in, wake pin generates one 55ms width high pulse to notify micro processor. 31 lx2 switch node of ch2. 32 pvd2 power input of ch2. to be continued
RT5002 6 ds5002-00 november 2011 www.richtek.com pin no. pin name pin function 33, 34 bat battery charge current output. 35, 36 sys system connect pin. connect this pin to system with a minimum 10 f ceramic capacitor to gnd. 37 vin supply voltage input. 38 rtcpwr rtc power output. 39 pvd1 power output of ch1. 40 lx1 switch node of ch1. 41 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum thermal dissipation.
RT5002 7 ds5002-00 november 2011 www.richtek.com function block diagram ch2 c-mode step-down + - pvd2 lx2 vddm ch1 c-mode step-up lx1 pvd1 vddm + - 0.8v ref fb1 i 2 c interface register file scl sda en1234 rtcpwr vddi power on/off sequence control rtc_ldo w / body diode control sys body diode control 0.8v ref fb2 ch3 c-mode step-down + - pvd3 lx3 vddm 0.8v ref fb3 ch4 c-mode step-down + - pvd4 lx4 vddm 0.8v ref fb4 ch7 step-up or current source + 31 level dimming v ref fb7 lx7 pvd7 vddm body diode control sys + - mod7 en7 en7_dim7 uvlo ss sys vddm uvlo li+ battery charger with appm vin tssel sys bat ts vp iseta bats usus vset isetl isetu iset timer ench vddi ch6 async inverting lx6 pvd6 vddm ch5 c-mode step-up + - 1.25v ref fb5 lx5 pvd5 vddm sys body diode control en56 vout6 en56 + - 0.6v ref fb6 1.8v ref vref gnd safe interrupt handler int eoc ts_fault pgood safe power plug-in wake up detector vin bat wake
RT5002 8 ds5002-00 november 2011 www.richtek.com charger function block diagram vin cc/cv/tr /dppm multi loop controller bat gnd ovp sleep mode logic bats iseta current set block uvlo timer i 2 c bank sys control circuit thermal circuit ssend2 isetl usus iset vset isetu i 2 c bank ts vp tssel nobat i 2 c bank int ench jeita pgood ts_fault eoc safe i 2 c bank
RT5002 9 ds5002-00 november 2011 www.richtek.com to be continued absolute maximum ratings (note 1) battery input voltage, bat --------------------------------------------------------------------------- ? 0.3v to 6v supply voltage, v ddm -------------------------------------------------------------------------------- ? 0.3v to 6v supply input voltage, vin ---------------------------------------------------------------------------- ? 0.3v to 28v bats, int ------------------------------------------------------------------------------------------------ ? 0.3v to 28v other pins ------------------------------------------------------------------------------------------------ ? 0.3v to 6v power switch (dc) : vout6 ---------------------------------------------------------------------------------------------------- ? 10v to 0.3v lx1, lx2, lx3, lx4 ------------------------------------------------------------------------------------- ? 0.3v to 6v pvd5, lx5 ------------------------------------------------------------------------------------------------ ? 0.3v to 24v pvd7, lx7 ------------------------------------------------------------------------------------------------ ? 0.3v to 17v lx6 --------------------------------------------------------------------------------------------------------- (pvd6 ? 16v) to (pvd6 + 0.3v) int continuous current ------------------------------------------------------------------------------- 20ma bat continuous current (total in two pin s) (note 2) ----------------------------------------- 2.5a power dissipation, p d @ t a = 25 c wqfn-40l 5x5 ----------------------------------------------------------------------------------------- 2.778w package thermal resistance (note 3) wqfn-40l 5x5, ja ------------------------------------------------------------------------------------ 36 c/w wqfn-40l 5x5, jc ----------------------------------------------------------------------------------- 7 c/w junction temperature ---------------------------------------------------------------------------------- 150 c lead temperature (soldering, 10 sec.) ------------------------------------------------------------ 260 c storage temperature range ------------------------------------------------------------------------- ? 65 c to 125 c esd susceptibility (note 4) hbm (human body mode) --------------------------------------------------------------------------- 2kv mm (ma chine mode) ----------------------------------------------------------------------------------- 200v recommended operating conditions (note 5) supply voltage, v ddm -------------------------------------------------------------------------------- 2.7v to 5.5v supply input voltage, vin (isetl = 1) ------------------------------------------------------------ 4.4v to 6v supply input voltage, vin (isetl = 0) ------------------------------------------------------------ 4.5v to 6v junction temperature range ------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range ------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics power converter unit : (v ddm = 4.2v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit supply voltage sys startup voltage for pmu v st 1.5 -- -- v sys uvlo (hysteresis low) -- 1.3 -- v sys uvlo hysteresis (gap) -- 0.2 -- v
RT5002 10 ds5002-00 november 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit vddm over voltage protection (ovp) (hysteresis high) 5.82 6.0 6.18 v vddm ovp hysteresis (gap) -- ? 0.25 -- v vddm uvlo (hysteresis high) 2.2 2.4 2.6 v vddm uvlo hysteresis (gap) -- 0.3 -- v supply current shutdown supply current i off all channels are off, v en1234 = 0v, v bat = 4.2v -- 10 20 a ch1 (sync-step-up) supply current into vddm i q1 no switching, v en1234 = 3.3v -- -- 800 a ch2 (syn-step-down) supply current into vddm i q2 no switching, v en1234 = 3.3v -- -- 800 a ch3 (syn-step-down) supply current into vddm i q3 no switching, v en1234 = 3.3v -- -- 800 a ch4 (syn-step-down) supply current into vddm i q4 no switching, v en1234 = 3.3v -- -- 800 a ch5 (syn-step-up) supply current into vddm i q5 non switching, en56 = 1 -- -- 800 a ch6 (inverting) supply current into vddm i q6 no switching, en56 = 1 -- -- 800 a ch7 (wled) in step-up mode supply current into vddm i q7b no switching, en7_dim7 [4:0] = 31, mod7 = 1 -- -- 800 a ch7 (wled) in current source mode supply current into vddm i q7c en7_dim7 [4:0] = 31, mod7 = 0 -- -- 800 a oscillator ch1, 2, 3, 4 operation frequency f osc 1800 2000 2200 khz ch5, 6, 7 operation frequency f osc2 ch7 in step-up mode 900 1000 1100 khz ch1 maximum duty cycle (step-up) v fb1 = 0.75v 80 83 86 % ch2 maximum duty cycle (step-down) v fb2 = 0.75v -- -- 100 % ch3 maximum duty cycle (step-down) v fb3 = 0.75v -- -- 100 % ch4 maximum duty cycle (step-down) v fb4 = 0.75v -- -- 100 % ch5 maximum duty cycle (step-up) v fb5 = 1.15v 91 93 97 % ch6 maximum duty cycle (inverting) v fb6 = 0.7v 91 93 97 % ch7 maximum duty cycle (step-up) v fb7 = 0.15v 91 93 97 % feedback, output regulation voltage, and output regulation current feedback regulation voltage @ fb1, fb2, fb3, fb4 0.788 0.8 0.812 v feedback regulation voltage @ fb5 1.237 1.25 1.263 v feedback regulation voltage @ fb6 (inverting) 0.58 0.6 0.62 v feedback regulation voltage @ fb7 (step-up mode and current source mode) en7_dim7 [4:0] = 31 0.237 0.25 0.263 v
RT5002 11 ds5002-00 november 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit reference vref output voltage v ref 1.77 1.8 1.83 v (vref-fb6) regulation voltage 1.182 1.2 1.218 v vref load regulation 0 a < iref < 200 a -- -- 10 mv power switch p-mosfet, v pvd1 = 3.3v -- 200 300 ch1 on resistance of mosfet n-mosfet, v pvd1 = 3.3v -- 150 250 m ch1 current limitation (step-up) 2.2 3 4 a p-mosfet, v pvd2 = 3.3v -- 200 300 ch2 on resistance of mosfet n-mosfet, v pvd2 = 3.3v -- 150 250 m ch2 current limitation (step-down) 1.4 1.8 2.2 a p-mosfet, v pvd3 = 3.3v -- 300 400 ch3 on resistance of mosfet n-mosfet, v pvd3 = 3.3v -- 300 400 m ch3 current limitation (step-down) 1.2 1.6 2 a p-mosfet, v pvd4 = 3.3v -- 300 400 ch4 on resistance of mosfet n-mosfet, v pvd4 = 3.3v -- 300 400 m ch4 current limitation (step-down) 1.2 1.6 2 a ch5 on resistance of p-mosfet v pvd5 = 16v -- 1.1 1.5 ch5 on resistance of n-mosfet v ddm = 3.3v -- 0.6 0.8 ch5 current limitation (step-up) n-mosfet 0.9 1.2 1.6 a ch6 on resistance of mosfet p-mosfet, v pvd6 = 3.3v -- 0.5 0.7 ch6 current limitation (inverting) p-mosfet 1 1.5 2 a ch7 on resistance of p-mosfet v pvd7 = 10v -- 2.0 3.0 ch7 on resistance of n-mosfet v ddm = 3.3v -- 0.9 1.1 ch7 current limitation (step-up) n-mosfet 0.6 0.8 1 a protection over voltage protection of pvd1 5.82 6.0 6.18 v over voltage protection of pvd5 20 22 24 v over voltage protection of vout6 -- ? 13 -- v over voltage protection of pvd7 (step-up mode) 14.2 15 16 v ch1 step-up under voltage protection of pvd1 -- v sys ? 0.8v -- v ch1/2/3/4 under voltage protection at v fbx < 0.4v after soft-start ends 0.35 0.4 0.45 v ch5 under voltage protection at v fb5 < 0.6v after soft-start ends 0.5 0.6 0.7 v ch6 under voltage protection at v fb6 > 1.2v after soft-start end 1.1 1.2 1.3 v ch1/2/3/4 overload protection at v fbx < 0.72v after fault delay (100ms) 0.65 0.7 0.75 v ch5 overload protection at v fb5 < 1.1v after fault delay (100ms) 1.05 1.1 1.15 v ch6 overload protection at v fb6 > 0.74v after fault delay (100ms) 0.69 0.74 0.79 v protection fault delay -- 100 -- ms
RT5002 12 ds5002-00 november 2011 www.richtek.com charger unit : (v in = 5v, v bat = 4v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit supply input vin under voltage lockout threshold v uvlo v in = 0v to 4v 3.1 3.3 3.5 v vin under voltage lockout hysteresis v uvlo v in = 4v to 0v -- 240 -- mv i sys = i bat = 0ma, ench = 0 (v bat > v regx ) -- 1 2 vin supply current i supply i sys = i bat = 0ma, ench = 1 (v bat > v regx ) -- 0.8 1.5 ma vin suspend current i usus v in = 5v, usus = 1 -- 195 300 a vin ? bat vos rising v os_h -- 200 300 mv vin ? bat vos falling v os_l 10 50 -- mv voltage regulation system regulation voltage v sys i sys = 800ma 4.3 4.4 4.5 v battery regulation voltage v reg1 0 to 85c, loading = 20ma, when vset = 1 4.16 4.2 4.23 v battery regulation voltage v reg2 0 to 85c, loading = 20ma, when vset = 0 4.01 4.05 4.08 v to be continued parameter symbol test conditions min typ max unit control logic-high 1.3 -- -- en1234, tssel input voltage threshold logic-low -- -- 0.4 v en1234, tssel sink current -- 1 6 a thermal protection thermal shutdown t sd -- 155 -- c thermal shutdown hysteresis t sd -- 20 -- c rtc ldo standby current v ddm = 4.2v -- 3 6 a v out (rtcpwr) i out = 0ma, v ddm = 4.2v 3.23 3.3 3.37 v max output current (current limit) v ddm = 4.2v 60 130 200 ma i out = 50ma -- -- 1000 i out = 10ma -- -- 150 dropout voltage i out = 3ma -- -- 60 mv wake up detector wake impulse high duration t wakeup vin or bat plug in, rtcpwr = 3.3v -- 55 -- ms high level v wake_h source current 0.5ma, rtcpwr = 3.3v -- rtcpwr ? 0.3 rtcpwr wake output low level v wake_l sink current ? 0.5ma, rtcpwr = 3.3 0 0.3 -- v vin threshold to wake up 3.1 3.3 3.5 v bat threshold to wake up -- 2.7 -- v bat threshold hysteresis to wake up -- 150 -- mv ?
RT5002 13 ds5002-00 november 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit appm regulation voltage v appm v sys ? v appm 120 200 280 mv dpm regulation voltage v dpm isetl = 0 4.3 4.4 4.5 v vin to sys mosfet on-resistance i vin = 1000ma -- 0.2 0.35 bat to sys mosfet on-resistance v bat = 4.2v, i sys = 1a -- 0.05 0.1 re-charge threshold v regchg battery regulation ? recharge level 60 100 140 mv bats divider ratio v bat = 4.2v 58.3 59.8 61.3 % current regulation iseta set voltage (fast charge phase) v iseta v bat = 4v, r iseta = 1k -- 2 -- v charge current setting range i chg 100 -- 1200 ma charge current accuracy1 i chg1 v bat = 4v, r iseta = 1k iset = 1 570 600 630 ma charge current accuracy2 i chg2 v bat = 3.8v, r iseta = 1k , iset = 0 285 300 315 ma isetl = 1 (1.5a mode) 1.2 1.5 1.8 a isetl = 0, isetu = 1 (500ma mode) 450 475 500 vin current limit i vin isetl = 0, isetu = 0 (100ma mode) 90 95 100 ma pre-charge bat pre-charge threshold v prech bat falling 2.7 2.8 2.9 v bat pre-charge threshold hysteresis v prech -- 200 -- mv pre-charge current i chg_pre v bat = 2v 5 10 15 % charge termination detection termination current ratio to fast charge (except usb 100 mode) i term isetl = 0, isetu = 1 isetl = 1, isetu = x 5 10 15 % termination current ratio to fast charge (usb100 mode) i term2 isetl = 0, isetu = 0 -- 3.3 -- % login input/output int pull down voltage v int i int = 5ma -- 200 -- mv protection thermal regulation t reg -- 125 -- c thermal shutdown temperature t sd -- 155 -- c thermal shutdown hysteresis t sd -- 20 -- c over voltage protection v ovp vin rising 6.25 6.5 6.75 v over voltage protection hysteresis v ovp v in = 7v to 5v, v ovp ? v ovp -- 100 -- mv output short circuit detection threshold v short v bat ? v sys -- 300 -- mv battery installation detection threshold at ts en1234 = h -- 90 -- % of vp time pre-charge fault time t pchg timer [3:0] = 0100, (1/8 x t fchg ) 1800 2250 2700 s fast charge fault time t fchg timer [3:0] = 0100 14400 18000 21600 s
RT5002 14 ds5002-00 november 2011 www.richtek.com parameter symbol test conditions min typ max unit pgood deglitch time t pgood time measured from vin : 0 to 5v 1 s rise-time to pgood = 1 in i 2 c register -- 1 -- s input over voltage blanking time t ovp -- 50 -- s pre-charge to fast-charge deglitch time t pf -- 25 -- ms fast-charge to pre-charge deglitch time t fp -- 25 -- ms termination deglitch time t termi -- 25 -- ms recharge deglitch time t rechg -- 100 -- ms input power loss to sys ldo turn-off d elay time t no_in -- 25 -- ms pack temperature fault detection deglitch time t ts -- 25 -- ms short circuit deglitch time t sh ort -- 250 -- s short circuit recovery time t sh ort-r -- 64 -- ms other vp regulation voltage v vp v ddm = 4.2v 3.234 3.3 3.366 v vp load regulation v vp vp source out 2ma -- -- -0.1 v vp under voltage lockout threshold falling threshold -- 0.8 -- v ts battery detect threshold v ts 2.75 2.85 2.95 v ntc rising threshold when tsse l = l (100k ntc) 73 74 75 low temperature trip point (0 c) v cold rising threshold when tssel = h (10k ntc) 59 60 61 % of vp low temperature trip point hysteresis (near 0 c) v cold -- 1 -- % of vp falling threshold when tssel = l 27 28 29 high temperature trip point (60 c) v hot falling threshold when tssel = h 37 38 39 % of vp high temperature trip point hysteresis (near 60 c) v hot -- 1 -- % of vp rising threshold when tsse l = l (100k ntc) 63 64 65 low temperature trip point (10 c) for jeita rising threshold when tssel = h (10k ntc) 53 54 55 % of vp low temperature trip point hysteresis (near 10 c) for jeita -- 1 -- % of vp falling threshold when tssel = l 34 35 36 high temperature trip point (45 c) for jeita falling threshold when tssel = h 39 40 41 % of vp high temperature trip point hysteresis (near 45 c) for jeita -- 1 -- % of vp
RT5002 15 ds5002-00 november 2011 www.richtek.com note 1. stresses listed as the above " absolute maximum ratings " may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. guaranteed by design. note 3. ja is measured in natural convection at t a = 25c on a high-effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 4. devices are esd sensitive. handling precaution is recommended. note 5. the device is not guaranteed to function outside its operating conditions. (v ddm = 3.3v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit logic inputs (sda scl) logic-high 2.0 -- -- sda, scl input threshold voltage logic-low -- -- 0.8 v i 2 c timing characteristics scl clock rate f scl v ddm = 3.3v -- -- 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 0.6 -- -- s low period of scl clock t low 1.3 -- -- s high period of scl clock t high 0.6 -- -- s set-up time for repeated start condition t su; sta 0.6 -- -- s data hold time t hd;dat 0 -- 0.9 s data set-up time t su; dat 100 -- -- ns set-up time for stop condition t su; sto 0.6 -- -- s bus free time between a stop and start condition t buf 1.3 -- -- s rise time of both sda and scl signals t r 20 -- 300 ns fall time of both sda and scl signals t f 20 -- 300 ns sda and scl output low sink current i ol sda or scl voltage = 0.4v 2 -- -- ma
RT5002 16 ds5002-00 november 2011 www.richtek.com typical operating characteristics ch1 step-up efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v sys = 2.7v v sys = 3v v sys = 3.3v v sys = 3.6v v sys = 3.9v v sys = 4.2v v sys = 4.4v v out = 5v, c out = 10 f x 2, l = 2.2 h ch2 step-down efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v out = 3.3v, c out = 10 f, l = 2.2 h v sys = 3.4v v sys = 3.7v v sys = 3.9v v sys = 4.2v v sys = 4.4v ch3 step-down efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v sys = 2.7v v sys = 3v v sys = 3.3v v sys = 3.6v v sys = 3.9v v sys = 4.2v v sys = 4.4v v out = 1.8v, c out = 10 f, l = 2.2 h ch4 step-down efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) v sys = 2.7v v sys = 3v v sys = 3.3v v sys = 3.6v v sys = 3.9v v sys = 4.2v v sys = 4.4v v out = 1v, c out = 10 f, l = 2.2 h ch5 step-up efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 1 10 100 output current (ma) efficiency (%) v sys = 2.7v v sys = 3v v sys = 3.3v v sys = 3.6v v sys = 3.9v v sys = 4.2v v sys = 4.4v v out = 15v, c out = 10 f x 2, l = 10 h ch6 inverting efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 110100 output current (ma) efficiency (%) v sys = 2.7v v sys = 3v v sys = 3.3v v sys = 3.6v v sys = 3.9v v sys = 4.2v v sys = 4.4v v out = ? 7v, c out = 10 f x 2, l = 10 h
RT5002 17 ds5002-00 november 2011 www.richtek.com ch7 efficiency vs. input voltage 0 10 20 30 40 50 60 70 80 90 100 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 input voltage (v) efficiency (%) 4wleds, i out = 25ma, c out = 1 f ch1 step-up output voltage vs. output current 4.90 4.95 5.00 5.05 5.10 5.15 5.20 0 100 200 300 400 500 600 load current (ma) output voltage (v) v sys = 3.4v v sys = 4.4v v out = 5v ch3 step-down output voltage vs. output current 1.795 1.800 1.805 1.810 1.815 1.820 1.825 0 100 200 300 400 500 600 load current (ma) output voltage (v) v out = 1.8v v sys = 4.4v v sys = 3.4v v sys = 2.7v ch4 step-down output voltage vs. output current 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 100 200 300 400 500 600 load current (ma) output voltage (v) v out = 1v v sys = 4.4v v sys = 3.4v v sys = 2.7v ch2 step-down output voltage vs. output current 3.28 3.29 3.30 3.31 3.32 3.33 3.34 0 100 200 300 400 500 600 load current (ma) output voltage (v) v sys = 3.6v v sys = 5v v out = 3.3v ch5 step-up output voltage vs. output current 14.8 14.9 15.0 15.1 15.2 15.3 15.4 0 20406080100 load current (ma) output voltage (v) v sys = 3.4v v sys = 4.4v v out = 15v
RT5002 18 ds5002-00 november 2011 www.richtek.com time (1ms/div) power off v out_ch1 (5v/div) v bat = 3.7v v out_ch2 (2v/div) v out_ch3 (2v/div) v out_ch4 (2v/div) ch6 inverting output voltage vs. output current -7.24 -7.22 -7.20 -7.18 -7.16 -7.14 -7.12 0 20 40 60 80 100 load current (ma) output voltage (v) v out = ? 7v v sys = 4.4v v sys = 3.4v v sys = 2.7v time (2.5ms/div) power on v out_ch1 (5v/div) v bat = 3.7v v out_ch2 (2v/div) v out_ch3 (2v/div) v out_ch4 (2v/div) time (5ms/div) power on v bat = 3.7v, seq56 = 1 v out_ch5 (10v/div) v out_ch6 (5v/div) time (2.5ms/div) power off v bat = 3.7v, seq56 = 1 v out_ch5 (10v/div) v out_ch6 (5v/div) time (5ms/div) power on v bat = 3.7v, seq56 = 0 v out_ch5 (10v/div) v out_ch6 (5v/div)
RT5002 19 ds5002-00 november 2011 www.richtek.com time (5ms/div) power off v bat = 3.7v, seq56 = 0 v out_ch5 (10v/div) v out_ch6 (5v/div) time (500ns/div) ch4 output voltage ripple lx4 (2v/div) v out_ch4_ac (5mv/div) i out = 400ma, c out = 10 f, l = 2.2 h v bat = 3.7v, v out = 1v time (500ns/div) ch3 output voltage ripple lx3 (2v/div) v out_ch3_ac (5mv/div) v bat = 3.7v, v out = 1.8v i out = 400ma, c out = 10 f, l = 2.2 h time (500ns/div) ch2 output voltage ripple lx2 (2v/div) v out_ch2_ac (5mv/div) v bat = 3.7v, v out = 3.3v i out = 400ma, c out = 10 f, l = 2.2 h time (500ns/div) ch1 output voltage ripple lx1 (2v/div) v out_ch1_ac (10mv/div) v bat = 3.7v, v out = 5v i out = 400ma, c out = 10 f x 2, l = 2.2 h time (1 s/div) ch5 output voltage ripple lx5 (5v/div) v out_ch5_ac (10mv/div) i out = 30ma, c out = 10 f x 2, l = 10 h v bat = 3.7v, v out = 15v
RT5002 20 ds5002-00 november 2011 www.richtek.com time (1 s/div) ch6 output voltage ripple lx6 (5v/div) v out_ch6_ac (10mv/div) i out = 50ma, c out = 10 f x 2, l = 10 h v bat = 3.7v, v out = ? 7v time (250 s/div) ch1 load transient response i out = 0a to 300ma, c out = 10 f x 2, l = 2.2 h i out (100ma/div) v out_ch1_ac (100mv/div) v bat = 3.7v, v out = 5v time (250 s/div) ch2 load transient response i out = 0a to 300ma, c out = 10 f, l = 2.2 h i out (100ma/div) v out_ch2_ac (50mv/div) v bat = 3.7v, v out = 3.3v time (250 s/div) ch3 load transient response i out = 100ma to 300ma, c out = 10 f, l = 2.2 h i out (100ma/div) v out_ch3_ac (10mv/div) v bat = 3.7v, v out = 3.3v time (250 s/div) ch4 load transient response i out = 100ma to 300ma, c out = 10 f, l = 2.2 h i out (100ma/div) v out_ch4_ac (10mv/div) v bat = 3.7v, v out = 1v time (250 s/div) ch5 load transient response i out = 10ma to 30ma, c out = 10 f x 2, l = 10 h i out (20ma/div) v out_ch5_ac (50mv/div) v bat = 3.7v, v out = 15v
RT5002 21 ds5002-00 november 2011 www.richtek.com time (25ms/div) charger on/off control from ench usb 500ma mode, v in = 5v, v bat = real battery i 2 c en (5v/div) v vp = 3.3v v bat (5v/div) i bat (500ma/div) time (250 s/div) ch6 load transient response c out = 10 f x 2, l = 10 h i out (20ma/div) v out_ch6_ac (10mv/div) v bat = 3.7v, v out = ? 7v, i out = 15ma to 50ma v sys (5v/div) v bat (10v/div) i in (500ma/div) v in (10v/div) time (100ms/div) v in hot-plug with ntc/without battery v in = 5v, v vp = 3.3v, r sys = 10 , isetl = 0 time (100ms/div) v in removal v in = 5v, v bat = real battery, v vp = 3.3v v sys (5v/div) v bat (10v/div) i bat (1a/div) v in (10v/div) r sys = 10 , isetl = 1 time (500ms/div) ts inserted / removed v in = 5v, v bat = real battery, v vp = 3.3v v bat (5v/div) v ts (2v/div) i bat (500ma/div) time (500ms/div) charger on/off control from v in usb 500ma mode, v in = 5v, v bat = real battery v in (5v/div) v bat (5v/div) i bat (500ma/div) v vp = 3.3v
RT5002 22 ds5002-00 november 2011 www.richtek.com v in - v sys dropout voltage vs. temperature 210 240 270 300 330 360 390 420 450 -50 -25 0 25 50 75 100 125 temperature (c) dropout voltage (mv) v in = 5v, i sys = 1a ovp threshold voltage vs. temperature 6.20 6.25 6.30 6.35 6.40 6.45 6.50 6.55 6.60 -50 -25 0 25 50 75 100 125 temperature (c) ovp threshold voltage (v) v in = 5v, v bat = 3.7v rising falling battery regulation voltage vs. temperature 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 -50 -25 0 25 50 75 100 125 temperature (c) battery regulation voltage (v ) v in = 5v, i sys = 0.5a time (100ms/div) v in hot-plug without ntc/battery v in = 5v, v vp = 3.3v, r sys = 10 , isetl = 0 v sys (5v/div) v bat (10v/div) i in (500ma/div) v in (10v/div) time (500ms/div) v in over voltage protection v bat = real battery, r sys = 10 , isetl = 1 v in (10v/div) v sys (10v/div) i bat (1a/div) v bat (10v/div) v in = 5v to 15v time (100ms/div) v in hot-plug with battery v bat = real battery, r sys = 10 , isetl = 1 v sys (5v/div) v bat (10v/div) i bat (1a/div) v in (10v/div) v in = 5v, v vp = 3.3v
RT5002 23 ds5002-00 november 2011 www.richtek.com v bat - v sys dropout voltage vs. temperature 50 55 60 65 70 75 80 85 90 -50 -25 0 25 50 75 100 125 temperature (c) dropout voltage (mv) v bat = 3.7v, i sys = 1a charge current vs. temperature 0 50 100 150 200 250 300 350 400 450 500 -50 -25 0 25 50 75 100 125 temperature (c) charge current (ma ) usb 500ma mode, v in = 5v v bat = 3.7v, v vp = 3.3v pre-charge current vs. battery voltage 110.0 112.5 115.0 117.5 120.0 122.5 125.0 127.5 130.0 2 2.2 2.4 2.6 2.8 3 battery voltage (v) pre-charge current (ma ) v in = 5v, r iseat = 0.5k fast-charge current vs. battery voltage 500 525 550 575 600 625 650 675 700 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 battery voltage (v) fast-charge current (ma ) v in = 5v, r iseat = 1k battery regulation voltage vs. temperature 4.100 4.125 4.150 4.175 4.200 4.225 4.250 4.275 4.300 -50 -25 0 25 50 75 100 125 temperature (c) battery regulation voltage (v ) v in = 5v
RT5002 24 ds5002-00 november 2011 www.richtek.com application information power converter unit the RT5002 is an integrated power system for digital still cameras and other small handheld devices. it includes six dc/dc converters as well as one wled driver, one rtc ldo, and a fully integrated single-cell li-ion battery charger ideal for portable applications. ch1 : step-up synchronous current mode dc/dc converter with internal power mosfets and compensation network. the p-mosfet body can be controlled to disconnect the load. it is suitable for providing power to the motor. ch2 to ch4 : step-down synchronous current mode dc/ dc converter with internal power mosfets and compensation network. these channels supply the power for i/o, dram, and core. they can be operated at 100% maximum duty cycle to extend battery operating voltage range. when the input voltage is close to the output voltage, the converter enters low dropout mode with low output ripple. ch5 : high voltage step-up synchronous current mode dc/dc converter with internal power mosfet and compensation network. the p-mosfet body can be controlled to disconnect the load. this channel supplies the ccd+ bias. ch6 : asynchronous inverting current mode dc/dc converter with internal power mosfet and compensation network. an external schottky diode is required. this channel supplies the ccd ? bias. ch7 : wled driver operating in either current source mode or synchronous step-up mode with internal power mosfet and compensation network. the operation mode is determined via the i 2 c interface. the p-mosfet body in step-up mode can be controlled to disconnect the load. ch1 to ch4 operate in pwm mode with 2mhz, while ch5 to ch7 operate in pwm mode with 1mhz switching frequency. rtc_ldo : 3.3v output ldo with low quiescent current and reverse leakage prevention from output node. output voltage design equation of ch1 to ch4 : the output voltage can be set by the following equation : v out = (1 + r h / r l ) x v fb where vfb is 0.8v typically, r h is r1, r3, r5, and r7 respectively for ch1 to 4, and r l is r2, r4, r6, and r8 respectively for ch1 to 4. output voltage design equation of ch5 : the output voltage can be set by the following equation : v out_ch5 = (1 + r9 / r10) x v fb5 where v fb5 is 1.25v typically. output voltage design equation of ch6 : the output voltage can be set by the following equation : v out_ch6 = ? (r11 / r12) x (1.2v) + 0.6v where r11 and r12 are the feedback resistors connected to fb6, 1.2v equals to (v ref ? v fb6 ), and 0.6v is the typical value of v fb6 . reference voltage the RT5002 provides a precise 1.8v reference voltage, v ref , with sourcing capability of 100 a. connect a 0.1 f ceramic capacitor from the v ref pin to gnd. reference voltage is enabled by i 2 c register bit en56 = 1. furthermore, this reference voltage is internally pulled to gnd at shutdown. ch5 and ch6 power sequence : ch5 and ch6 are enabled together via i 2 c interface and their power on sequence can be chosen via i 2 c register setting.
RT5002 25 ds5002-00 november 2011 www.richtek.com address b[7] (msb) b[6] b[5] b[4] b[3] b[2] b[1] b[0] (lsb) meaning mod7 seq56 en56 en7_dim7 [4:0] default 0 0 0 0 0 0 0 0 0x0 read/write r/w r/w r/w r/w r/w r/w r/w r/w 1 ch7 in step-up mode mod7 0 ch7 in current source mode 1 ch5/6 power on sequence is ch5 ch6, power off sequence is ch6 ch5 seq56 0 ch5/6 power on sequence is ch6 ch5, power off sequence is ch5 ch6 1 enable (turn on) ch5 and ch6 by preset sequence en56 0 disable (turn off) ch5 and ch6 by preset enable ch7 and define fb7 regulation voltage 00000 ch7 turn off en7_dim7 [4:0] 00001 to 11111 ch7 turn on and dimming ratio : vfb7 = en7_dim7 [4:0] / 31 x 0.25v ch7 : wled driver ch7 is a wled driver that can operate in either current source mode or synchronous step-up mode, as determined by the i 2 c interface. when ch7 works in current source mode, it sources an led current out of lx7 pin and regulates the current by fb7 voltage. the led current is defined by the fb7 voltage as well as the external resistor seq56 = 1 seq56 = 0 between fb7 and gnd. the fb7 regulation voltage can be set in 31 steps from 8mv to 250mv, typically, via i 2 c interface. if ch7 works in synchronous step-up mode, it integrates synchronous step-up mode with an internal mosfet and internal compensation to output a voltage up to 15v. the led current is also set via an external resistor and fb7 regulation voltage. ch5 v out 10ms 18ms ch6 v out constant current pre-charge. wait until vout6 > -0.12v 5ms en56 ch5 v out 10ms 16ms ch6 v out constant current pre- charge. wait until vout5 < 0.5v 5ms en56 2ms
RT5002 26 ds5002-00 november 2011 www.richtek.com ch7 wled current dimming control if ch7 is in synchronous step-up mode or current source mode, the wled current is set by an external resistor. regardless of the mode, dimming is always controlled by the i 2 c interface. the wled current can be set by the following equations : iled (ma) = [250mv / r (w)] x en7_dim7 [4:0] / 31 where r is the current sense resistor from fb7 to gnd and en7_dim7 [4:0] / 31 ratio refers to the i 2 c control register file. it is recommended that ch7 input power connects to the node sys in order to prevent abnormal ch7 start-up. vddm bootstrap to support bootstrap function, the RT5002 includes a power selection circuit which selects between sys and pvd1 to create the internal node voltage vddi and vddm. vddm is the power of the RT5002 pmu control circuits which must be connected to an external decoupling capacitor by way of the vddm pin. vddi is the power input of the rtc ldo. the output pvd1 of ch1 can bootstrap vddm and vddi. the RT5002 includes uvlo circuits to monitor vddm and sys voltage status. rtc ldo the RT5002 provides a 3.3v output ldo for real-time clock. the ldo features low quiescent current (3 m a) and high output voltage accuracy. this ldo is always on, even when the system is shut down. for better stability, it is recommended to connect a 0.1 m f capacitor to the rtcpwr pin. the rtc ldo includes pass transistor body diode control to avoid the rtcpwr node from back- charging into the input node vddi. power on/off sequence for ch1 to ch4 en1234 will turn on/off ch1 to ch4 in preset sequence. ch1 to ch4 power on sequence is : when en1234 goes high, ch1 will turn on first. 3.5ms after ch1 is turned on, ch3 will turn on. 3.5ms after ch3 is turned on, ch4 will turn on. 3.5ms after ch4 is turned on, ch2 will turn on. ch1 to ch4 power off sequence is : when en1234 goes low, ch2 will turn off first and internally discharge output. when fb2 < 0.1v, ch4 will turn off and also internally discharge output via the lx4 pin. when fb4 < 0.1v, ch3 will turn off and internally discharge output via the lx3 pin. likewise, when fb3 < 0.1v, ch1 will turn off and discharge output. after fb1 < 0.1v, ch1 to 4 shutdown sequence will be completed. charger unit the RT5002 includes a li-ion battery charger with automatic power path management. the charger is designed to operate in below modes : pre-charge mode when the output voltage is lower than 2.8v, the charging current will be reduced to a fast-charge current ratio set by r iseta to protect the battery life-time. fast-charge mode when the output voltage is higher than 3v, the charging current will be equal to the fast-charge current set by r iseta . constant voltage mode when the output voltage is near 4.2v and the charging current falls below the termination current, after a deglitch time check of 25ms, the charger will become disabled. re-charge mode when the chip is in charge termination mode, the charging current gradually goes down to zero. however, once the voltage of the battery drops to below 4.1v, there will be a deglitch time of 100ms and then the charging current will resume again.
RT5002 27 ds5002-00 november 2011 www.richtek.com address b[7] (msb) b[6] b[5] b[4] b[3] b[2] b[1] b[0] (lsb) meaning isetu isetl usus nobat eoc pgood ts_fault safe default 1 0 0 0 0 0 0 0 0x2 read/write r/w r/w r/w r r r r r isetu and isetl : set vin input current limit isetu isetl vin input current limit 0 0 95ma 1 0 475ma x 1 1.5a usus : vin suspend control input 1 suspend usus 0 no suspend battery installation detection 1 no battery installed (ts > 90% of vp) nobat 0 bat installed (ts < 90% of vp) end_of_charge status 1 charging done or recharging after termination eoc 0 during charging vin power good status 0 v in < v uvlo 0 v uvlo < v in < v bat + v os_h 1 v bat + v os_h < v in < v ovp pgood 0 v in > v ovp temperature sensing status 1 ts is at fault (too cold, too hot) or vp triggers uvlo. ts_fault 0 ts and vp are normal. charger safety timer status 1 safety timer expired. safe 0 otherwise i 2 c register for charging status setting
RT5002 28 ds5002-00 november 2011 www.richtek.com charger state bit eoc bit pgood bit safe charging 0 1 0 charging suspended by thermal loop 0 1 0 safety timers expired 0 1 1 charging done 1 1 0 recharging after termination 1 1 0 ic disabled or no valid input power 0 0 0 charge state wake-up detector wake-up detector detects vin or bat plug-in events. once one of them plug-in, wake pin asserts one 55ms-width high pulse. the timing diagram is shown below. wake timing diagram battery installation detection RT5002 also detect ts voltage to judge the battery installation status. if pmu is enabled but ts voltage > 90% of vp node voltage, RT5002 would set the bit nobat = 1 in i 2 c register bank 0x2. end_of_charge (eoc) status the bit eoc in i 2 c register bank 0x2 can show the eoc status. if eoc = 1, the charger is in eoc state. suspend mode set usus = 1, and the charge will enter suspend mode. in suspend mode, i usus (max) < 300 m a. battery sense when pmu is turned on, bats = 59.8% x bat, the RT5002 detects the battery level from bats voltage level. interrupt indicator the RT5002 provides the interrupt indicator output pin (int). int is an open drain pin. when the status bits (pgood, ts_fault, eoc, safe) of i 2 c register address 0x2 toggle, the int is set to be low. after reg 0x2 is read or pmu turn off, int goes high. 4 0.4ms bats v out2 vin wake bat 55ms 55ms 3.3v 2.7v
RT5002 29 ds5002-00 november 2011 www.richtek.com charging current decision the charge current can be set according to the following equations : chg1 iseta chg_fast iseta chg2 iseta chg_fast iseta chg_prechg_fast if iset = 1 (for i) v i = 300 r if iset = 0 (for i) v i = 150 r i = 10%i address b[7] (msb) b[6] b[5] b[4] b[3] b[2] b[1] b[0] (lsb) meaning timer [3:0] ench jeita iset vset default 0 1 0 0 0 0 0 0 0x1 read/write r/w r/w r/w r/w r/w r/w r/w r/w vin power good status timer [3:0] 0000 to 1111 fast charge timeout period : t fchg = (timer [3:0] + 1) hours. (iset = 1) pre-charge timeout period : t pchg = t fchg / 8 1 disable charger ench 0 enable charger 1 charger operation controlled by i 2 c bits vset and iset jeita 0 charger operation automatically in jeita temperature standard half charge current set input 1 for i chg1 : time = t fchg iset 0 for i chg2 : time = 2 x t fchg , i chg2 = i chg1 / 2 battery regulation set input 1 battery regulation voltage is 4.2v vset 0 battery regulation voltage is 4.05v chg1 fchg chg2 fchg if iset = 1 (for i) time = t if iset = 0 (for i) time = 2t time fault during the fast charge phase, several events may increase the charging time. for example, the system load current may have activated the appm loop which reduces the available charging current or the device has entered thermal regulation because the ic junction temperature has exceeded t reg . however, once the duration exceeds the fault time, the register 0x2 bit [0] will be changed from 0 to 1, and the charge current will be reduced to about 1ma. time fault release methods : (1) re-plug power (2) toggle en (3) enter/exit suspend mode (4) remove battery (5) ovp
RT5002 30 ds5002-00 november 2011 www.richtek.com case 2 : tssel = h (for 10k w ntc) : figure 2 0.6 x vp + - + - vp too cold too hot ts r1 r2 r ntc vp 0.38 x vp cold cold hot hot coldhot hot cold cold cold cold r2 + r = 0.6 r+r1+r2 r2 + r = 0.38 r+r1+r2 form (1), (2) rr r1 = 0.9 r2 = 0.6r1r if r2 < 0 r = 0.6 r+r1 form (3) r r1 = r 0.6 - - - too cold temperature r cold = r ntc too hot temperature r hot = r ntc (1) (2) (3) battery pack temperature monitoring the battery pack temperature monitoring function can be realized by connecting the ts pin to an external negative temperature coefficient (ntc) thermistor to prevent over temperature condition. charging is suspended when the voltage at the ts pin is out of normal operating range. the internal timer is then paused, but the value is maintained. when the ts pin voltage returns back to normal operating range, charging will resume and the safe charge timer will continue to count down from the point where it was suspended. the 3.3v at vp pin is buffered by the RT5002 once it is in charging state or its pmu part is enabled. for 100k w ntc thermistor, the input pin, tssel, should be connected to gnd. for 10k w ntc thermistor, the input pin, tssel, should be connected to vin. tssel determines the ts threshold levels for 0 c and 60 c. it also defines the ts threshold levels used in jeita operation. the choosing method of r1 and r2 to meet battery temperature monitoring is shown below : case 1 : tssel = l (for 100k w ntc) : 0.74 x vp + - + - vp too cold too hot ts r1 r2 r ntc vp 0.28 x vp figure 1 too cold temperature r cold = r ntc too hot temperature r hot = r ntc cold cold hot hot coldhot hot cold cold cold cold r2 + r = 0.74 r+r1+r2 r2 + r = 0.28 r+r1+r2 form (1), (2) rr r1 = 2.457 r2 = 0.389r1r if r2 < 0 r = 0.74 r+r1 form (3) r r1 = r 0.74 - - - (1) (2) (3) jeita battery temperature standard cv regulation voltage will change at the following battery temperature ranges : 0 c to 10 c and 45 c to 60 c. cc regulation current will change at the following battery temperature ranges : 0 c to 10 c and 45 c to 60 c.
RT5002 31 ds5002-00 november 2011 www.richtek.com the control temperature used in jeita operation : the above calculation gives r1 and r2. jeita control thresholds for full charging current and 4.2v regulation voltage are at ts/vp ratio = 40% and 54% (for tssel = h), 35% and 64% (for tssel = l). with the ratio, the corresponding ntc thermistor resistances from the resistors in the voltage divider circuit can be obtained. according to the ntc resistances, the corresponding temperatures can be found. the two temperatures are the control temperatures used in jeita operation. power switch for the charger, there are three power scenarios : (1) when a battery and an external power supply (usb or adapter) are connected simultaneously : if the system load requirements exceed that of the input current limit, the battery will be used to supplement the current to the load. however, if the system load requirements are less than that of the input current limit, the excess power from the external power supply will be used to charge the battery. (2) when only the battery is connected to the system : the battery provides the power to the system. (3) when only an external power supply is connected to the system : the external power supply provides the power to the system. input dpm mode for the charger, the input voltage is monitored when usb100 or usb500 is selected. if the input voltage is lower than vdpm, the input current limit will be reduced to stop the input voltage from dropping any further. this can prevent the ic from damaging improperly configured or inadequately designed usb sources. appm mode once the sum of the charging and system load currents becomes higher than the maximum input current limit, the sys pin voltage will be reduced. when the sys pin voltage is reduced to vappm, the RT5002 will automatically operate in appm mode. in this mode, the charging current is reduced while the sys current is increased to maintain system output. in appm mode, the battery termination function is disabled. battery supplement mode short circuit protect in appm mode, the sys voltage will continue to drop if the charge current is zero and the system load increases beyond the input current limit. when the sys voltage decreases below the battery voltage, the battery will kick in to supplement the system load until the sys voltage rises above the battery voltage. while in supplement mode, there is no battery supplement current regulation. however, a built-in short circuit protection feature is available to prevent any abnormal current situations. while the battery is supplementing the load, if the difference between the battery and sys voltage becomes more than the short circuit threshold voltage, sys will be disabled. after a short circuit recovery time, t short_r , the counter will be restarted. in supplement mode, the battery termination function is disabled. note that for the battery supply mode exit condition, vbat- vsys < 0v. thermal regulation and thermal shutdown the charger provides a thermal regulation loop function to monitor the device temperature. if the die temperature rises above the regulation temperature, treg, the charge current will automatically be reduced to lower the die temperature. however, in certain circumstances (such as high vin, heavy system load, etc.) even with the thermal loop in place, the die temperature may still continue to increase. in this case, if the temperature rises above the thermal shutdown threshold, tsd, the internal switch between vin and sys will be turned off. the switch between the battery and sys will remain on, however, to allow continuous battery power to the load. once the die temperature decreases by d tsd, the internal switch between vin and sys will be turned on again and the device returns to normal thermal regulation. the internal thermal feedback circuitry regulates the die temperature to optimize the charge rate for all ambient temperatures.
RT5002 32 ds5002-00 november 2011 www.richtek.com figure 3 appm profile 1.5a mode : 1a 0 -1a 2a 3a -2a -3a 5v 4.4v 4.2v 4.0v i bat i sys i vin t1 t2 t3 t4 t5 t6 t7 v bat v in v sys v appm i sys v sys i vin i bat t1, t7 0 sys regulation voltage chg_max chg_max t2, t6 < i vin_oc - chg_max sys regulation voltage i sys + chg_max chg_max t3, t5 > i vin_oc - chg_max < i vin_oc auto charge voltage threshold v in_oc v in_oc - i sys t4 > i vin_oc v bat - i bat x r ds(on) v in_oc i sys - i vin_oc 4.16 to 4.2 to 4.23v - 40 c to 85 c battery voltage charging current v prech v rech i term2 if isetl = 0, isetu = 0 i termi = 3.3% x i chg_fast if isetl = 1, isetu = 1 isetl = 0, isetu = x i termi = 10% x i chg_fast time i chg_pre = 10% x i chg_fast
RT5002 33 ds5002-00 november 2011 www.richtek.com 0.25a 0 -0.25a 0.5a 0.75a -0.5a -0.75a 5v 4.2v 4.0v i bat i sys i usb t1 t2 t3 t4 t5 t6 t7 v bat v usb v sys v appm 4.4v i sys v sys i usb i bat t1, t7 0 sys regulation voltage chg_max chg_max t2, t6 < i vin_oc (usb) - chg_max sys regulation voltage i sys + chg_max chg_max t3, t5 > i vin_oc (usb) - chg_max < i vin_oc (usb) auto charge voltage threshold i vin_oc (usb) i vin_oc (usb) - i sys t4 > i vin_oc (usb) v bat - i bat x r ds(on) i vin_oc (usb) i sys - i vin_oc (usb) usb 500ma mode : vset vs. v reg , iset vs. i chg 4.16 to 4.2 to 4.23v 4.01 to 4.05 to 4.08v i chg +/-5% 0.5 x i chg +/-5% vset iset v reg i chg for jeita battery temperature standard : cv regulation voltage will change at the following battery temp ranges 0 c to 10 c and 45 c to 60 c cc regulation current will change at the following battery temp ranges 0 c to 10 c and 45 c to 60 c 0 c 10 c 45 c 60 c temperature +/- 2 c 4.16 to 4.2 to 4.23v 4.01 to 4.05 to 4.08v i chg +/- 5% 0.5 x i chg +/- 5% 0.5 x i chg +/- 5% temperature +/- 2 c 4.01 to 4.05 to 4.08v when jeita = 1, v reg and i chg are set by the bits vset and iset, respectively. when jeita = 0, v reg and i chg follows jeita temperature standard.
RT5002 34 ds5002-00 november 2011 www.richtek.com RT5002 operation state diagram for charging operation state diagram for ts pin (tssel = l) any state 74% x v vp < v ts < 2.85v or v ts < 28% x v vp no yes ts fault state i chg = 0a ts_fault = 1 v ts > 2.85v no yes battery remove state i chg = 0a reset timer and nobat = 1 any state or v in < v uvlo , or v in > v ovp , or v in - v bat < v os_h or usus = 1 or ench = 1 charger disable standby state sleep state v in C v bat > v os_h v bat > 3v pre-charge state i chg_pre = 10% x i chg_fast time > t pchg fast-charge state if iset = 1 i chg_fast = (v iseta / r iseta ) x 300 if iset = 0 i chg_fast = (v iseta / r iseta ) x 150 if vset = 1 check v bat > 4.1v if vset = 0 check v bat > 3.95v time > t termi = 25msec charge done state eoc = 1 & i chg = 0a if vset = 1 check v bat < 4.1v if vset = 0 check v bat < 3.95v re-charge state timer-out state safe = 1 & i chg to 1ma time > t fchg v uvlo < v in < v ovp & ench = 0 & usus = 0 no yes yes no yes no yes no yes yes no yes yes no yes no isetl = 0 & isetu = 1 isetl = 1 & isetu = x check i chg < 10% x i chg_fast if isetl = 0 & isetu = 0 check i chg < 3.3% x i chg_fast if
RT5002 35 ds5002-00 november 2011 www.richtek.com i 2 c interface the RT5002 i 2 c slave address is by default = 0011000 (7bits), but if customers request, the slave address can be changed to 0011010 (7bits). the i 2 c interface supports fast mode (bit rate up to 400kb/s). the write or read bit stream (n>=1) is shown below : i 2 c register file address b[7] (msb) b[6] b[5] b[4] b[3] b[2] b[1] b[0] (lsb) meaning mod7 seq56 en56 en7_dim7 [4:0] default 0 0 0 0 0 0 0 0 0x0 read/write r/w r/w r/w r/w r/w r/w r/w r/w meaning timer [3:0] ench jeita iset vset default 0 1 0 0 0 0 0 0 0x1 read/write r/w r/w r/w r/w r/w r/w r/w r/w meaning isetu isetl usus nobat eoc pgood ts_fault safe default 1 0 0 0 0 0 0 0 0x2 read/write r/w r/w r/w r r r r r reset after en1234 = l and pmu shutdown completely. sda scl t f t low t hd;sta t hd;dat t high t su;dat t su;sta t hd;sta t sp t buf t su;sto p s t r s r s t f t r driven by master, driven by slave (RT5002), start, repeat start stop, s sr p write n bytes s slave address 0 a register address a msb data 1 lsb a msb data 2 lsb a data for address = m + n - 1 assume address = m data for address = m data for address = m + 1 r/w read n bytes r/w assume address = m data for address = m data for address = m + n - 1 data for address = m+1 s slave address 0 a register address sr a slave address 1 a a msb data 1 lsb msb data 2 lsb a msb data n lsb a p msb data n lsb a p
RT5002 36 ds5002-00 november 2011 www.richtek.com figure 4. derating curves for RT5002 package 0.00 0.40 0.80 1.20 1.60 2.00 2.40 2.80 3.20 0 25 50 75 100 125 ambient temperature ( c) maximum power dissipation (w) 1 four-layer pcb thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) - t a ) / q ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and q ja is the junction to ambient thermal resistance. for recommended operating condition specifications of the RT5002, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, q ja , is layout dependent. for wqfn- 40l 5x5 packages, the thermal resistance, q ja , is 36 c/ w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c - 25 c) / (36 c/w) = 2.778w for wqfn-40l 5x5 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, q ja . for the RT5002 package, the derating curve in figure 4 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. layout considerations for the best performance of the RT5002, the following pcb layout guidelines must be strictly followed. } place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. } keep the main power traces as wide and short as possible. } the switching node area connected to lx and inductor should be minimized for lower emi. } place the feedback components as close as possible to the fb pin and keep these components away from the noisy devices. } connect the gnd and exposed pad to a strong ground plane for maximum thermal dissipation and noise protection. } the connection of riseta should be isolated from other noisy traces. a short wire is recommended to prevent emi and noise coupling.
RT5002 37 ds5002-00 november 2011 www.richtek.com figure 5. pcb layout guide l1 c4 c22 r4 r1 c12 r10 r3 c9 l2 c21 d5 d4 c5 l7 l5 c13 r5 c18 c6 l3 c7 c17 r7 r16 c15 l4 r13 c20 c3 c1 l6 c2 d1 d2 c14 vout_ch1 vout_ch4 vout_ch5 vout_ch3 vout_ch2 sys gnd gnd vout_ch7 gnd sys lx should be connected to inductor by wide and short trace, keep sensitive compontents away from this trace. connect the exposed pad to a ground plane. place the feedback components as close as possible to the fb pin and keep away from noisy devices. input/output capacitors must be placed as close as possible to the input/output pins. r9 c19 v o u t _ c h 6 d3 c24 s y s sys s y s sys c10 r8 c8 sys c11 r iseta r17 r11 r12 r6 the riseta connection copper area should be minimized and kept far away from noise sources. bypass cap gnd gnd gnd gnd gnd gnd gnd r2 g n d c16 r ntc int fb7 vddm fb4 pvd4 lx4 bats pvd7 lx7 fb1 wake lx5 tssel fb3 pvd3 lx3 en1234 pvd5 fb5 fb2 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 i s e t a t s v p s d a s c l p v d 6 l x 6 v o u t 6 f b 6 v r e f l x 1 p v d 1 r t c p w r v i n s y s s y s b a t b a t p v d 2 l x 2 20 19 18 17 16 15 14 13 12 11 31 32 33 34 35 36 37 38 39 40 41 gnd
RT5002 38 ds5002-00 november 2011 www.richtek.com protection type threshold (typical) refer to electrical spec. protection methods ic shutdown delay time reset method sys uvlo sys < 1.3v pmu shutdown. no-delay vddm power reset or en1234 pin set to low ovp vddm > 6v automatic reset at vddm < 5.75v 100ms vddm power reset or en1234 pin set to low vddm uvlo vddm < 2.4v pmu shutdown. no-delay vddm power reset or en1234 pin set to low current limit n-mosfet current > 3a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddm power reset or en1234 pin set to low pvd1 ovp pvd1 > 6v n-mosfet off, p-mosfet off. no-delay vddm power reset or en1234 pin set to low pvd1 uvp pvd1 < (vsys - 0.8v) or pvd1 < 1.28v after soft-start end. n-mosfet off, p-mosfet off. 100ms vddm power reset or en1234 pin set to low fb1 uvp fb1 < 0.4v after pre-charge n-mosfet off, p-mosfet off no-delay vddm power reset or en1234 pin set to low ch1 step-up fb1 over load (ol) fb1 < 0.7v pmu shutdown when ol occur each cycle until 100ms. 100ms vddm power reset or en1234 pin set to low current limit p-mosfet current > 1.8a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddm power reset or en1234 pin set to low fb2 uvp fb2 < 0.4v after soft-start end. n-mosfet off, p-mosfet off. 100ms vddm power reset or en1234 pin set to low ch2 step-down fb2 over load fb2 < 0.7v pmu shutdown when ol occur each cycle until 100ms. 100ms vddm power reset or en1234 pin set to low current limit p-mosfet current > 1.6a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddm power reset or en1234 pin set to low fb3 uvp fb3 < 0.4v after soft-start end. n-mosfet off, p-mosfet off. 100ms vddm power reset or en1234 pin set to low ch3 step-down fb3 over load fb3 < 0.7v pmu shutdown when ol occur each cycle until 100ms. 100ms vddm power reset or en1234 pin set to low current limit p-mosfet current > 1.6a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddm power reset or en1234 pin set to low fb4 uvp fb4 < 0.4v after soft-start end. n-mosfet off, p-mosfet off. 100ms vddm power reset or en1234 pin set to low ch4 step-down fb4 over load fb4 < 0.7v pmu shutdown when ol occur each cycle until 100ms. 100ms vddm power reset or en1234 pin set to low to be continued
RT5002 39 ds5002-00 november 2011 www.richtek.com protection type threshold (typical) refer to electrical spec. protection methods ic shutdown delay time reset method current limit n-mosfet current > 1.2a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddm power reset or en1234 pin set to low pvd5 ovp pvd5 > 22v n-mosfet off, p-mosfet off. no-delay vddm power reset or en1234 pin set to low fb5 uvp fb5 < 0.6v after soft-start end. n-mosfet off, p-mosfet off. 100ms vddm power reset or en1234 pin set to low fb5 over load fb5 < 1.1v pmu shutdown when ol occur each cycle until 100ms. 100ms vddm power reset or en1234 pin set to low ch5 step-up pvd5 uvp pvd5 < (vsys - 0.2v) n-mosfet off, p-mosfet off. 100ms vddm power reset or en1234 pin set to low current limit p-mosfet current > 1.5a p-mosfet off. automatic reset at next clock cycle. 100ms vddm power reset or en1234 pin set to low pvd6 ovp pvd6 < -13v p-mosfet off. no-delay vddm power reset or en1234 pin set to low fb6 uvp fb6 > 1.2v p-mosfet off. 100ms vddm power reset or en1234 pin set to low ch6 async inverting fb6 over load fb6 > 0.74v pmu shutdown when ol occur each cycle until 100ms. 100ms vddm power reset or en1234 pin set to low current limit n-mosfet current > 0.8a n-mosfet off, p-mosfet off. automatic reset at next clock cycle. 100ms vddm power reset or en1234 pin set to low ch7 wled pvd7 ovp pvd7 > 15v n-mosfet off, p-mosfet off. shutdown ch7 by self no-delay vddm power reset and reg0x00[4 to 0] = 00000 reset or en1234 pin set to low thermal thermal shutdown temperature > 155 c all channels stop switching no-delay vddm power reset or en1234 pin set to low protection type threshold (typical) refer to electrical spec. protection methods charger shutdown delay time reset method vin uvlo vin < 3.3v no-charge no-delay no latch vin vin ovp vin > 6.5v no-charge no-delay no latch
RT5002 40 ds5002-00 november 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property infringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications is assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 4.950 5.050 0.195 0.199 d2 3.250 3.500 0.128 0.138 e 4.950 5.050 0.195 0.199 e2 3.250 3.500 0.128 0.138 e 0.400 0.016 l 0.350 0.450 0.014 0.018 w-type 40l qfn 5x5 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. detail a pin #1 id and tie bar mark options 1 1 2 2 d e d2 e2 l b a a1 a3 e 1 see detail a

▲Up To Search▲

Price & Availability of RT5002

	To Download RT5002 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .